//-----------------------------------------------------
// Design Name : Register File v. 1.0.1
// File Name   : RegisterFile.v
// Function    : Serve as a 16-bit register file
//-----------------------------------------------------
// Change Log:
// 	2008 NOV 7 8:38 PM:	Made names verbose.
//-----------------------------------------------------

module RegisterFile  #(parameter WIDTH = 16, REGBITS = 4)
                (input                clk, 
                 input                regwrite, 
                 input  [REGBITS-1:0] readAddress, readWriteAddress,  
                 input  [WIDTH-1:0]   writeData, 
                 output [WIDTH-1:0]   readData, readWriteData);

   reg  [WIDTH-1:0] RAM [(1<<REGBITS)-1:0];

   // Two-port register file
   // read two ports combinationally
   // write 2nd port address on rising edge of clock
   // register 0 hardwired to 0
	//
	// On reading from the register file regwrite = 0
	// and registers at addresses ra, rwa appear on the
	// outputs.
	//
	// On a write to the register file regwrite = 1 and
	// register at address rwa gets the value in wd and
	// the outputs and ra are ignored.

   always @(posedge clk)
      if (regwrite) RAM[readWriteAddress] <= writeData;	
	
   assign readData = readAddress ? RAM[readAddress] : 0;
   assign readWriteData = readWriteAddress ? RAM[readWriteAddress] : 0;
	
endmodule

